Image processing architectures typically involve a number of processing stages for executing image processing, including enhancing algorithms such as half toning, depletion, error diffusion and edge smoothing. The conventional approach is that a portion of image data is completely processed by each stage before the next portion of image data can be processed. The conventional architecture makes extensive use of external memory to store and retrieve intermediate data. The intermediate data is retrieved for processing in successive stages, which necessitates frequent access of a large amount of external memory. This, in turn, dictates a need for expensive, high-speed memory. Furthermore, the large amount of data processed by the intermediate stages prevents design of a simple pipeline with internal memory. One such conventional arrangement is shown in FIG. 1.
Conventional image processing architectures, such as are used in computer printer engines, generally exhibit a number of other disadvantages, such as requiring the addition of preprocessing stages that progressively increase total processing time and reduce image processing speed.
The present invention seeks to overcome or at least reduce one or more of the problems in the prior art.